/*
 * Device Tree Generator version: 1.1
 *
 * (C) Copyright 2007-2012 Xilinx, Inc.
 * (C) Copyright 2007-2012 Michal Simek
 * (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd
 *
 * Michal SIMEK <monstr@monstr.eu>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 * CAUTION: This file is automatically generated by libgen.
 * Version: Xilinx EDK 14.5 EDK_P.58f
 * Today is: Thursday, the 25 of July, 2013; 13:09:33
 *
 * XPS project directory: device-tree_bsp_0
 */

/dts-v1/;
/ {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "xlnx,virtex440", "xlnx,virtex";
	dcr-parent = <&ppc440_0>;
	model = "Xilinx PPC Virtex440";
	aliases {
		ethernet0 = &hard_ethernet_mac_ETHERNET;
		serial0 = &rs232;
	} ;
	chosen {
		bootargs = "console=ttyS0,115200 mem=128M memmap=128M@128M ip=on root=/dev/nfs rw nfsroot=192.168.40.1:/data/attpc/ram,tcp ipmtu=8982";
		linux,stdout-path = "/plb@0/serial@83e00000";
	} ;
	cpus {
		#address-cells = <1>;
		#cpus = <0x1>;
		#size-cells = <0>;
		ppc440_0: cpu@0 {
			#address-cells = <1>;
			#size-cells = <1>;
			clock-frequency = <400000000>;
			compatible = "PowerPC,440", "ibm,ppc440";
			d-cache-line-size = <0x20>;
			d-cache-size = <0x8000>;
			dcr-access-method = "native";
			dcr-controller ;
			device_type = "cpu";
			i-cache-line-size = <0x20>;
			i-cache-size = <0x8000>;
			model = "PowerPC,440";
			reg = <0>;
			timebase-frequency = <400000000>;
			xlnx,apu-control = <0x2000>;
			xlnx,apu-udi-0 = <0x0>;
			xlnx,apu-udi-1 = <0x0>;
			xlnx,apu-udi-10 = <0x0>;
			xlnx,apu-udi-11 = <0x0>;
			xlnx,apu-udi-12 = <0x0>;
			xlnx,apu-udi-13 = <0x0>;
			xlnx,apu-udi-14 = <0x0>;
			xlnx,apu-udi-15 = <0x0>;
			xlnx,apu-udi-2 = <0x0>;
			xlnx,apu-udi-3 = <0x0>;
			xlnx,apu-udi-4 = <0x0>;
			xlnx,apu-udi-5 = <0x0>;
			xlnx,apu-udi-6 = <0x0>;
			xlnx,apu-udi-7 = <0x0>;
			xlnx,apu-udi-8 = <0x0>;
			xlnx,apu-udi-9 = <0x0>;
			xlnx,dcr-autolock-enable = <0x1>;
			xlnx,dcu-rd-ld-cache-plb-prio = <0x0>;
			xlnx,dcu-rd-noncache-plb-prio = <0x0>;
			xlnx,dcu-rd-touch-plb-prio = <0x0>;
			xlnx,dcu-rd-urgent-plb-prio = <0x0>;
			xlnx,dcu-wr-flush-plb-prio = <0x0>;
			xlnx,dcu-wr-store-plb-prio = <0x0>;
			xlnx,dcu-wr-urgent-plb-prio = <0x0>;
			xlnx,dma0-control = <0x0>;
			xlnx,dma0-plb-prio = <0x0>;
			xlnx,dma0-rxchannelctrl = <0x1010000>;
			xlnx,dma0-rxirqtimer = <0x3ff>;
			xlnx,dma0-txchannelctrl = <0x1010000>;
			xlnx,dma0-txirqtimer = <0x3ff>;
			xlnx,dma1-control = <0x0>;
			xlnx,dma1-plb-prio = <0x0>;
			xlnx,dma1-rxchannelctrl = <0x1010000>;
			xlnx,dma1-rxirqtimer = <0x3ff>;
			xlnx,dma1-txchannelctrl = <0x1010000>;
			xlnx,dma1-txirqtimer = <0x3ff>;
			xlnx,dma2-control = <0x0>;
			xlnx,dma2-plb-prio = <0x0>;
			xlnx,dma2-rxchannelctrl = <0x1010000>;
			xlnx,dma2-rxirqtimer = <0x3ff>;
			xlnx,dma2-txchannelctrl = <0x1010000>;
			xlnx,dma2-txirqtimer = <0x3ff>;
			xlnx,dma3-control = <0x0>;
			xlnx,dma3-plb-prio = <0x0>;
			xlnx,dma3-rxchannelctrl = <0x1010000>;
			xlnx,dma3-rxirqtimer = <0x3ff>;
			xlnx,dma3-txchannelctrl = <0x1010000>;
			xlnx,dma3-txirqtimer = <0x3ff>;
			xlnx,endian-reset = <0x0>;
			xlnx,generate-plb-timespecs = <0x1>;
			xlnx,icu-rd-fetch-plb-prio = <0x0>;
			xlnx,icu-rd-spec-plb-prio = <0x0>;
			xlnx,icu-rd-touch-plb-prio = <0x0>;
			xlnx,interconnect-imask = <0xffffffff>;
			xlnx,mplb-allow-lock-xfer = <0x1>;
			xlnx,mplb-arb-mode = <0x0>;
			xlnx,mplb-awidth = <0x20>;
			xlnx,mplb-counter = <0x500>;
			xlnx,mplb-dwidth = <0x80>;
			xlnx,mplb-max-burst = <0x8>;
			xlnx,mplb-native-dwidth = <0x80>;
			xlnx,mplb-p2p = <0x0>;
			xlnx,mplb-prio-dcur = <0x2>;
			xlnx,mplb-prio-dcuw = <0x3>;
			xlnx,mplb-prio-icu = <0x4>;
			xlnx,mplb-prio-splb0 = <0x1>;
			xlnx,mplb-prio-splb1 = <0x0>;
			xlnx,mplb-read-pipe-enable = <0x1>;
			xlnx,mplb-sync-tattribute = <0x0>;
			xlnx,mplb-wdog-enable = <0x1>;
			xlnx,mplb-write-pipe-enable = <0x1>;
			xlnx,mplb-write-post-enable = <0x1>;
			xlnx,num-dma = <0x1>;
			xlnx,pir = <0xf>;
			xlnx,ppc440mc-addr-base = <0x0>;
			xlnx,ppc440mc-addr-high = <0xfffffff>;
			xlnx,ppc440mc-arb-mode = <0x0>;
			xlnx,ppc440mc-bank-conflict-mask = <0x0>;
			xlnx,ppc440mc-control = <0x8060008f>;
			xlnx,ppc440mc-max-burst = <0x8>;
			xlnx,ppc440mc-prio-dcur = <0x2>;
			xlnx,ppc440mc-prio-dcuw = <0x3>;
			xlnx,ppc440mc-prio-icu = <0x4>;
			xlnx,ppc440mc-prio-splb0 = <0x1>;
			xlnx,ppc440mc-prio-splb1 = <0x0>;
			xlnx,ppc440mc-row-conflict-mask = <0x0>;
			xlnx,ppcdm-asyncmode = <0x0>;
			xlnx,ppcds-asyncmode = <0x0>;
			xlnx,user-reset = <0x0>;
			DMA0: sdma@80 {
				compatible = "xlnx,ll-dma-1.00.a";
				dcr-reg = < 0x80 0x11 >;
				interrupt-parent = <&xps_intc_0>;
				interrupts = < 4 2 5 2 >;
			} ;
		} ;
	} ;
	mpmc_core_0: memory@0 {
		device_type = "memory";
		reg = < 0x0 0x10000000 >;
	} ;
	plb_v46_0: plb@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "xlnx,plb-v46-1.05.a", "xlnx,plb-v46-1.00.a", "simple-bus";
		ranges ;
		cm_modes: gpio@8181c800 {
			#gpio-cells = <2>;
			compatible = "xlnx,xps-gpio-2.00.a", "xlnx,xps-gpio-1.00.a";
			gpio-controller ;
			reg = < 0x8181c800 0x200 >;
			xlnx,all-inputs = <0x0>;
			xlnx,all-inputs-2 = <0x0>;
			xlnx,dout-default = <0x0>;
			xlnx,dout-default-2 = <0x0>;
			xlnx,family = "virtex5";
			xlnx,gpio-width = <0x4>;
			xlnx,gpio2-width = <0x20>;
			xlnx,interrupt-present = <0x0>;
			xlnx,is-dual = <0x0>;
			xlnx,tri-default = <0xffffffff>;
			xlnx,tri-default-2 = <0xffffffff>;
		} ;
		cobocontrol_0: cobocontrol@20000000 {
			compatible = "xlnx,cobocontrol-1.00.a";
			reg = < 0x20000000 0x1000 >;
			xlnx,as0a0cinvert = <0x1>;
			xlnx,as0a1cinvert = <0x0>;
			xlnx,as0a2cinvert = <0x1>;
			xlnx,as0a3cinvert = <0x0>;
			xlnx,as0ca0invert = <0x1>;
			xlnx,as0ca1invert = <0x0>;
			xlnx,as0ca2invert = <0x1>;
			xlnx,as0ca3invert = <0x1>;
			xlnx,as1a0cinvert = <0x1>;
			xlnx,as1a1cinvert = <0x0>;
			xlnx,as1a2cinvert = <0x1>;
			xlnx,as1a3cinvert = <0x0>;
			xlnx,as1ca0invert = <0x1>;
			xlnx,as1ca1invert = <0x1>;
			xlnx,as1ca2invert = <0x1>;
			xlnx,as1ca3invert = <0x0>;
			xlnx,as2a0cinvert = <0x0>;
			xlnx,as2a1cinvert = <0x1>;
			xlnx,as2a2cinvert = <0x0>;
			xlnx,as2a3cinvert = <0x1>;
			xlnx,as2ca0invert = <0x1>;
			xlnx,as2ca1invert = <0x1>;
			xlnx,as2ca2invert = <0x1>;
			xlnx,as2ca3invert = <0x1>;
			xlnx,as3a0cinvert = <0x0>;
			xlnx,as3a1cinvert = <0x1>;
			xlnx,as3a2cinvert = <0x1>;
			xlnx,as3a3cinvert = <0x1>;
			xlnx,as3ca0invert = <0x1>;
			xlnx,as3ca1invert = <0x0>;
			xlnx,as3ca2invert = <0x1>;
			xlnx,as3ca3invert = <0x1>;
			xlnx,ckp0invert = <0x1>;
			xlnx,ckp1invert = <0x1>;
			xlnx,ckp2invert = <0x0>;
			xlnx,ckp3invert = <0x1>;
			xlnx,family = "virtex5";
			xlnx,include-dphase-timer = <0x1>;
		} ;
		cobodata_0: cobodata@10000000 {
			compatible = "xlnx,cobodata-1.00.a";
			reg = < 0x10000000 0x800 >;
			xlnx,cobodataidx = <0x0>;
			xlnx,family = "virtex5";
			xlnx,include-dphase-timer = <0x1>;
			xlnx,oa0invert = <0x0>;
			xlnx,oa1invert = <0x1>;
			xlnx,ob0invert = <0x1>;
			xlnx,ob1invert = <0x0>;
			xlnx,oc0invert = <0x0>;
			xlnx,oc1invert = <0x1>;
			xlnx,od0invert = <0x0>;
			xlnx,od1invert = <0x0>;
			xlnx,pi-addr-width = <0x20>;
			xlnx,pi-be-width = <0x8>;
			xlnx,pi-data-width = <0x40>;
			xlnx,pi-rdwdaddr-width = <0x4>;
		} ;
		cobodata_1: cobodata@10000800 {
			compatible = "xlnx,cobodata-1.00.a";
			reg = < 0x10000800 0x800 >;
			xlnx,cobodataidx = <0x1>;
			xlnx,family = "virtex5";
			xlnx,include-dphase-timer = <0x1>;
			xlnx,oa0invert = <0x0>;
			xlnx,oa1invert = <0x1>;
			xlnx,ob0invert = <0x0>;
			xlnx,ob1invert = <0x1>;
			xlnx,oc0invert = <0x1>;
			xlnx,oc1invert = <0x1>;
			xlnx,od0invert = <0x1>;
			xlnx,od1invert = <0x0>;
			xlnx,pi-addr-width = <0x20>;
			xlnx,pi-be-width = <0x8>;
			xlnx,pi-data-width = <0x40>;
			xlnx,pi-rdwdaddr-width = <0x4>;
		} ;
		cobodata_2: cobodata@10001000 {
			compatible = "xlnx,cobodata-1.00.a";
			reg = < 0x10001000 0x800 >;
			xlnx,cobodataidx = <0x2>;
			xlnx,family = "virtex5";
			xlnx,include-dphase-timer = <0x1>;
			xlnx,oa0invert = <0x1>;
			xlnx,oa1invert = <0x0>;
			xlnx,ob0invert = <0x1>;
			xlnx,ob1invert = <0x1>;
			xlnx,oc0invert = <0x1>;
			xlnx,oc1invert = <0x1>;
			xlnx,od0invert = <0x0>;
			xlnx,od1invert = <0x0>;
			xlnx,pi-addr-width = <0x20>;
			xlnx,pi-be-width = <0x8>;
			xlnx,pi-data-width = <0x40>;
			xlnx,pi-rdwdaddr-width = <0x4>;
		} ;
		cobodata_3: cobodata@10001800 {
			compatible = "xlnx,cobodata-1.00.a";
			reg = < 0x10001800 0x800 >;
			xlnx,cobodataidx = <0x3>;
			xlnx,family = "virtex5";
			xlnx,include-dphase-timer = <0x1>;
			xlnx,oa0invert = <0x1>;
			xlnx,oa1invert = <0x0>;
			xlnx,ob0invert = <0x0>;
			xlnx,ob1invert = <0x1>;
			xlnx,oc0invert = <0x0>;
			xlnx,oc1invert = <0x1>;
			xlnx,od0invert = <0x1>;
			xlnx,od1invert = <0x1>;
			xlnx,pi-addr-width = <0x20>;
			xlnx,pi-be-width = <0x8>;
			xlnx,pi-data-width = <0x40>;
			xlnx,pi-rdwdaddr-width = <0x4>;
		} ;
		flash: flash@30000000 {
			bank-width = <2>;
			compatible = "xlnx,xps-mch-emc-3.01.a", "cfi-flash";
			reg = < 0x30000000 0x2000000 >;
			xlnx,family = "virtex5";
			xlnx,include-datawidth-matching-0 = <0x1>;
			xlnx,include-datawidth-matching-1 = <0x0>;
			xlnx,include-datawidth-matching-2 = <0x0>;
			xlnx,include-datawidth-matching-3 = <0x0>;
			xlnx,include-negedge-ioregs = <0x0>;
			xlnx,include-plb-ipif = <0x1>;
			xlnx,include-wrbuf = <0x1>;
			xlnx,max-mem-width = <0x10>;
			xlnx,mch-native-dwidth = <0x20>;
			xlnx,mch-splb-awidth = <0x20>;
			xlnx,mch-splb-clk-period-ps = <0x2710>;
			xlnx,mch0-accessbuf-depth = <0x10>;
			xlnx,mch0-protocol = <0x0>;
			xlnx,mch0-rddatabuf-depth = <0x10>;
			xlnx,mch1-accessbuf-depth = <0x10>;
			xlnx,mch1-protocol = <0x0>;
			xlnx,mch1-rddatabuf-depth = <0x10>;
			xlnx,mch2-accessbuf-depth = <0x10>;
			xlnx,mch2-protocol = <0x0>;
			xlnx,mch2-rddatabuf-depth = <0x10>;
			xlnx,mch3-accessbuf-depth = <0x10>;
			xlnx,mch3-protocol = <0x0>;
			xlnx,mch3-rddatabuf-depth = <0x10>;
			xlnx,mem0-width = <0x10>;
			xlnx,mem1-width = <0x20>;
			xlnx,mem2-width = <0x20>;
			xlnx,mem3-width = <0x20>;
			xlnx,num-banks-mem = <0x1>;
			xlnx,num-channels = <0x0>;
			xlnx,pagemode-flash-0 = <0x0>;
			xlnx,pagemode-flash-1 = <0x0>;
			xlnx,pagemode-flash-2 = <0x0>;
			xlnx,pagemode-flash-3 = <0x0>;
			xlnx,priority-mode = <0x0>;
			xlnx,synch-mem-0 = <0x0>;
			xlnx,synch-mem-1 = <0x0>;
			xlnx,synch-mem-2 = <0x0>;
			xlnx,synch-mem-3 = <0x0>;
			xlnx,synch-pipedelay-0 = <0x2>;
			xlnx,synch-pipedelay-1 = <0x2>;
			xlnx,synch-pipedelay-2 = <0x2>;
			xlnx,synch-pipedelay-3 = <0x2>;
			xlnx,tavdv-ps-mem-0 = <0x1d4c0>;
			xlnx,tavdv-ps-mem-1 = <0x3a98>;
			xlnx,tavdv-ps-mem-2 = <0x3a98>;
			xlnx,tavdv-ps-mem-3 = <0x3a98>;
			xlnx,tcedv-ps-mem-0 = <0x1d4c0>;
			xlnx,tcedv-ps-mem-1 = <0x3a98>;
			xlnx,tcedv-ps-mem-2 = <0x3a98>;
			xlnx,tcedv-ps-mem-3 = <0x3a98>;
			xlnx,thzce-ps-mem-0 = <0x88b8>;
			xlnx,thzce-ps-mem-1 = <0x1b58>;
			xlnx,thzce-ps-mem-2 = <0x1b58>;
			xlnx,thzce-ps-mem-3 = <0x1b58>;
			xlnx,thzoe-ps-mem-0 = <0x1b58>;
			xlnx,thzoe-ps-mem-1 = <0x1b58>;
			xlnx,thzoe-ps-mem-2 = <0x1b58>;
			xlnx,thzoe-ps-mem-3 = <0x1b58>;
			xlnx,tlzwe-ps-mem-0 = <0x88b8>;
			xlnx,tlzwe-ps-mem-1 = <0x0>;
			xlnx,tlzwe-ps-mem-2 = <0x0>;
			xlnx,tlzwe-ps-mem-3 = <0x0>;
			xlnx,tpacc-ps-flash-0 = <0x61a8>;
			xlnx,tpacc-ps-flash-1 = <0x61a8>;
			xlnx,tpacc-ps-flash-2 = <0x61a8>;
			xlnx,tpacc-ps-flash-3 = <0x61a8>;
			xlnx,twc-ps-mem-0 = <0x1d4c0>;
			xlnx,twc-ps-mem-1 = <0x3a98>;
			xlnx,twc-ps-mem-2 = <0x3a98>;
			xlnx,twc-ps-mem-3 = <0x3a98>;
			xlnx,twp-ps-mem-0 = <0x1d4c0>;
			xlnx,twp-ps-mem-1 = <0x2ee0>;
			xlnx,twp-ps-mem-2 = <0x2ee0>;
			xlnx,twp-ps-mem-3 = <0x2ee0>;
			xlnx,xcl0-linesize = <0x4>;
			xlnx,xcl0-writexfer = <0x1>;
			xlnx,xcl1-linesize = <0x4>;
			xlnx,xcl1-writexfer = <0x1>;
			xlnx,xcl2-linesize = <0x4>;
			xlnx,xcl2-writexfer = <0x1>;
			xlnx,xcl3-linesize = <0x4>;
			xlnx,xcl3-writexfer = <0x1>;
		} ;
		hard_ethernet_mac: xps-ll-temac@87000000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "xlnx,compound";
			ranges ;
			hard_ethernet_mac_ETHERNET: ethernet@87000000 {
				compatible = "xlnx,xps-ll-temac-2.03.a", "xlnx,xps-ll-temac-1.01.b", "xlnx,xps-ll-temac-1.00.a";
				device_type = "network";
				interrupt-parent = <&xps_intc_0>;
				interrupts = < 3 2 >;
				llink-connected = <&DMA0>;
				local-mac-address = [ 00 0a 35 00 00 00 ];
				reg = < 0x87000000 0x40 >;
				xlnx,avb = <0x0>;
				xlnx,bus2core-clk-ratio = <0x1>;
				xlnx,mcast-extend = <0x0>;
				xlnx,phy-type = <0x5>;
				xlnx,phyaddr = <0x1>;
				xlnx,rxcsum = <0x1>;
				xlnx,rxfifo = <0x8000>;
				xlnx,rxvlan-strp = <0x0>;
				xlnx,rxvlan-tag = <0x0>;
				xlnx,rxvlan-tran = <0x0>;
				xlnx,stats = <0x0>;
				xlnx,temac-type = <0x0>;
				xlnx,txcsum = <0x1>;
				xlnx,txfifo = <0x8000>;
				xlnx,txvlan-strp = <0x0>;
				xlnx,txvlan-tag = <0x0>;
				xlnx,txvlan-tran = <0x0>;
			} ;
		} ;
		interrupt_0: interrupt@60040000 {
			compatible = "xlnx,interrupt-1.00.a";
			interrupt-parent = <&xps_intc_0>;
			interrupts = < 0 2 >;
			reg = < 0x60040000 0x1000 >;
			xlnx,family = "virtex5";
			xlnx,include-dphase-timer = <0x1>;
		} ;
		leds: gpio@81814000 {
			#gpio-cells = <2>;
			compatible = "xlnx,xps-gpio-2.00.a", "xlnx,xps-gpio-1.00.a";
			gpio-controller ;
			reg = < 0x81814000 0x200 >;
			xlnx,all-inputs = <0x0>;
			xlnx,all-inputs-2 = <0x0>;
			xlnx,dout-default = <0x0>;
			xlnx,dout-default-2 = <0x0>;
			xlnx,family = "virtex5";
			xlnx,gpio-width = <0x10>;
			xlnx,gpio2-width = <0x20>;
			xlnx,interrupt-present = <0x0>;
			xlnx,is-dual = <0x0>;
			xlnx,tri-default = <0xffffffff>;
			xlnx,tri-default-2 = <0xffffffff>;
		} ;
		pll_0: pll@81812000 {
			compatible = "xlnx,pll-1.00.a";
			reg = < 0x81812000 0x40 >;
			xlnx,family = "virtex5";
			xlnx,include-dphase-timer = <0x1>;
			xlnx,mwire-clkdiv = <0x4>;
		} ;
		rs232: serial@83e00000 {
			clock-frequency = <100000000>;
			compatible = "xlnx,xps-uart16550-3.00.a", "ns16550a";
			current-speed = <115200>;
			device_type = "serial";
			interrupt-parent = <&xps_intc_0>;
			interrupts = < 2 2 >;
			reg = < 0x83e00000 0x10000 >;
			reg-offset = <0x1003>;
			reg-shift = <2>;
			xlnx,external-xin-clk-hz = <0x17d7840>;
			xlnx,family = "virtex5";
			xlnx,has-external-rclk = <0x0>;
			xlnx,has-external-xin = <0x0>;
			xlnx,is-a-16550 = <0x1>;
		} ;
		timer: timer@83c00000 {
			compatible = "xlnx,xps-timer-1.02.a", "xlnx,xps-timer-1.00.a";
			interrupt-parent = <&xps_intc_0>;
			interrupts = < 1 0 >;
			reg = < 0x83c00000 0x10000 >;
			xlnx,count-width = <0x20>;
			xlnx,family = "virtex5";
			xlnx,gen0-assert = <0x1>;
			xlnx,gen1-assert = <0x1>;
			xlnx,one-timer-only = <0x0>;
			xlnx,trig0-assert = <0x1>;
			xlnx,trig1-assert = <0x1>;
		} ;
		wdt: xps-timebase-wdt@83a00000 {
			clock-frequency = <100000000>;
			compatible = "xlnx,xps-timebase-wdt-1.02.a", "xlnx,xps-timebase-wdt-1.00.a";
			reg = < 0x83a00000 0x10000 >;
			xlnx,family = "virtex5";
			xlnx,wdt-enable-once = <0x1>;
			xlnx,wdt-interval = <0x1e>;
		} ;
		xps_bram_if_cntlr_0: xps-bram-if-cntlr@ffff0000 {
			compatible = "xlnx,xps-bram-if-cntlr-1.00.b", "xlnx,xps-bram-if-cntlr-1.00.a";
			reg = < 0xffff0000 0x10000 >;
			xlnx,family = "virtex5";
		} ;
		xps_intc_0: interrupt-controller@81800000 {
			#interrupt-cells = <0x2>;
			compatible = "xlnx,xps-intc-2.01.a", "xlnx,xps-intc-1.00.a";
			interrupt-controller ;
			reg = < 0x81800000 0x10000 >;
			xlnx,kind-of-intr = <0x2>;
			xlnx,num-intr-inputs = <0x6>;
		} ;
	} ;
} ;
